The present invention relates to a method of forming a semiconductor memory device, and more particularly to a method of forming a semiconductor memory device such as a flash memory having source/drain diffusion layers with a reduced resistance.
The semiconductor memory device such as a flash memory has been subjected to the requirement for shrinkage of cell. In order to scale down the cell, a source diffusion layer is formed by self-alignment technique using a gate electrode as a mask. This self-aligned source technique is disclosed in Japanese patent publication No. 63-41224.
In recent years, a further scaling down of the cell has been on the requirement. Under this circumstances, a trench isolation technique has been attractive for scaling down the isolation to the diffusion layers. A conventional method of forming a semiconductor memory device having a trench isolation structure will be described.
FIG. 1A is a fragmentary plane view illustrative of a semiconductor memory device having a trench isolation structure in a first step involved in a conventional fabrication method. FIG. 1B is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a first step involved in a conventional fabrication method, taken along a Ixe2x80x94I line of FIG. 1A. FIG. 1C is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a first step involved in a conventional fabrication method, taken along an IIxe2x80x94II line of FIG. 1A. FIG. 1D is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a first step involved in a conventional fabrication method, taken along an IIIxe2x80x94III line of FIG. 1A.
With reference to FIGS. 1A, 1B, 1C and 1D, a trench isolation technique is used to form a plurality of trench isolations 102 in a semiconductor substrate 100 thereby to define a plurality of diffusion layers 101 in the semiconductor substrate 100, wherein each of the diffusion layers 101 are defined between the adjacent two of the trench isolations 102. The trench isolations 102 have a stripe shape in plane view and a trench shape in sectional view. The trench isolations 102 extend in a first horizontal direction and in parallel to each other at a constant pitch.
FIG. 2A is a fragmentary plane view illustrative of a semiconductor memory device having a trench isolation structure in a second step involved in a conventional fabrication method. FIG. 2B is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a second step involved in a conventional fabrication method, taken along a Ixe2x80x94I line of FIG. 2A. FIG. 2C is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a second step involved in a conventional fabrication method, taken along an IIxe2x80x94II line of FIG. 2A, FIG. 2D is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a second step involved in a conventional fabrication method, taken along an IIIxe2x80x94III line of FIG. 2A.
A gate insulation film is formed over surfaces of the diffusion layers 101. A floating gate electrode layer 104 is then formed on the gate insulation film. Laminations of the gate insulation film and the floating gate electrode layer are patterned to form gate insulation films 103 which cover the diffusion layers 101 and the floating gate electrodes 104 on the gate insulation films 103. The floating gate electrodes 104 extend in the first horizontal direction and in parallel to each other at the constant pitch.
FIG. 3A is a fragmentary plane view illustrative of a semiconductor memory device having a trench isolation structure in a third step involved in a conventional fabrication method. FIG. 3B is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a third step involved in a conventional fabrication method, taken along a Ixe2x80x94I line of FIG. 3A. FIG. 3C is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a third step involved in a conventional fabrication method, taken along an IIxe2x80x94II line of FIG. 3A. FIG. 3D is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a third step involved in a conventional fabrication method, taken along an IIIxe2x80x94III line of FIG. 3A.
An inter-layer insulator 105 is formed over the substrate 100, so that the inter-layer insulator 105 covers the floating gate electrodes 104, wherein the inter-layer insulator 105 comprises laminations of a silicon oxide film, a silicon nitride film and a silicon oxide film. Control gate electrodes 106 are formed over the substrate 100 so that the control gate electrodes 106 are stripe shaped and extend in a second direction perpendicular to the first direction along which the trench isolations 102 extend. The control gate electrodes 106 comprises laminations of a polysilicon layer 106a and a tungsten silicide layer 106b on the polysilicon layer 106a. 
FIG. 4A is a fragmentary plane view illustrative of a semiconductor memory device having a trench isolation structure in a fourth step involved in a conventional fabrication method. FIG. 4B is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a fourth step involved in a conventional fabrication method, taken along a Ixe2x80x94I line of FIG. 4A. FIG. 4C is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a fourth step involved in a conventional fabrication method, taken along an IIxe2x80x94II line of FIG. 4A. FIG. 4D is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a fourth step involved in a conventional fabrication method, taken along an IIIxe2x80x94III line of FIG. 4A.
A photo-resist pattern 107 is selectively formed which has an opening which is positioned over a gap between the adjacent two of the control gate electrode 106 and also over confronting half sides of the adjacent two of the control gate electrode 106. The photo-resist pattern 107 and the control gate electrodes 106 are used as masks to carry out an etching to the trench isolations 102, so that trench grooves are formed. The photo-resist pattern 107 is removed.
FIG. 5A is a fragmentary plane view illustrative of a semiconductor memory device having a trench isolation structure in a fifth step involved in a conventional fabrication method. FIG. 5B is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a fifth step involved in a conventional fabrication method, taken along a Ixe2x80x94I line of FIG. 5A FIG. 5C is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a fifth step involved in a conventional fabrication method, taken along an IIxe2x80x94II line of FIG. 5A. FIG. 5D is a fragmentary cross sectional elevation view illustrative of a semiconductor memory device having a trench isolation structure in a fifth step involved in a conventional fabrication method, taken along an IIIxe2x80x94III line of FIG. 5A.
An ion-implantation of an impurity such as arsenic is carried out in a vertical direction to the surface of the substrate to form source diffusion layers 108 in upper regions of the diffusion regions 101. Etched portions of the isolations have a trench structure, for which reason it is difficult for the vertical ion-implantation to introduce the impurity such as arsenic to the side surfaces 101a of the trench structure, whereby an increase in resistance of the source diffusion layer 108 is caused. The increase in resistance of the source diffusion layer 108 deteriorates high speed performance of the cells of the flash memory, and speeds of writing and reading operations.
In the above circumstances, it had been required to develop a novel method of forming a semiconductor memory device free from the above problem.
Accordingly, it is an object of the present invention to provide a novel method of forming a semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel method of forming a semiconductor memory device without increase in resistance of a source diffusion layer.
It is a still further object of the present invention to provide a novel method of forming a semiconductor memory device by introducing a sufficient amount of impurity into side surfaces of trench structures.
The present invention provides a method of forming a diffusion layer which extends on bottoms and side walls of trench grooves as well as on top portions of ridged portions separating the trench grooves, and the trench grooves being separated by ridged portions of the substrate so that the trench grooves and the ridged portions are aligned between adjacent two of gate electrode structures, the method comprising the steps of carrying out a first ion-implantation in a vertical direction to introduce an impurity into the bottoms of the trench grooves and into top portions of the ridged portions by use of gate electrode structures; forming side wall insulation films on side walls of the gate electrode structures; and carrying out a second ion-implantation in an oblique direction with a rotation of the substrate by use of the gate electrode structures and the side walls.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.